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Wafer-level CNT growth on CMOS substrates

January 29, 2011 by AboutNanoWires.com · Leave a Comment 

Addressable micro-heaters integrate carbon nanotubes without hampering on-chip electronics
nanotechweb.org: lab talk

Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

October 15, 2010 by AboutNanoWires.com · Leave a Comment 

Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.

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Integrated Chemical Microsensor Systems in CMOS Technology

August 25, 2010 by AboutNanoWires.com · Leave a Comment 

Integrated Chemical Microsensor Systems in CMOS Technology

This book, “Integrated Chemical Microsensor Systems in CMOS Technology”, provides a comprehensive treatment of the highly interdisciplinary field of CMOS chemical microsensor systems. It is targeted at students, scientists and engineers who are interested in gaining an introduction to the field of chemical sensing since all the necessary fundamental knowledge is included. However, as it provides detailed information on all important issues related to the realization of chemical microsensors in CMOS technology, it also addresses experts well familiar with the field.

After a brief introduction, the fundamentals of chemical sensing are presented. Fabrication and processing steps that are commonly used in the semiconductor industry are then detailed followed by a short description of the microfabrication techniques, and of the CMOS substrate and materials. Thereafter, a comprehensive overview of semiconductor-based and CMOS-based transducer structures for chemical sensors is given. CMOS-technology is then introduced as platform technology, which enables the integration of these microtransducers with the necessary driving and signal conditioning circuitry on the same chip. In a next section, the development of monolithic multisensor arrays and fully developed microsystems with on-chip sensor control and standard interfaces is described. A short section on packaging shows that techniques from the semiconductor industry can be applied to chemical microsensor packaging. The book concludes with a brief outlook on future developments, such as the realization of more complex integrated microsensor systems and methods to interface biological materials, such as cells, with CMOS microelectronics.

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Design for Manufacturability and Yield for Nano-Scale CMOS

August 13, 2010 by AboutNanoWires.com · 1 Comment 

Design for Manufacturability and Yield for Nano-Scale CMOS

As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility.

Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

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Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

June 28, 2010 by AboutNanoWires.com · Leave a Comment 

Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding. The authors present three examples of ultralow-power systems based on FD-SOI technology, providing every reader with practical knowledge on the technology and the circuits.

List Price: $ 149.00

Price: $ 98.04

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