Leakage in Nanometer CMOS Technologies

Leakage in Nanometer CMOS Technologies

The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

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Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level.

The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit.

At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

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Leakage in Nanometer CMOS Technologies

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The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction.

Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles.  The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions.

Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions.  Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

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